1. Technical Field
The present disclosure relates to burn-in tests of integrated circuits like EEPROM memories, at the end of manufacture. These tests include in particular subjecting, during some time, an integrated circuit to unfavorable operating constraints, to cause a failure of the circuit if it has some manufacture defects. That way, the integrated circuits passing such tests have a failure rate which may reach low values.
2. Description of the Related Art
One of the main causes of failure of an EEPROM memory is gate oxide breakdown of transistors which may be subjected to a relatively high voltage. The rate of failure tends to increase with memory miniaturization. In an EEPROM memory, such high voltage transistors are present in bit line latches, gate control latches and word line selection latches, as well as in each memory cell and in gate control switches of a group of memory cells. FIG. 1 schematically shows a conventional EEPROM memory. In FIG. 1, the memory MEM1 comprises a memory array CELM comprising memory cells distributed into lines and columns transverse to lines. Line and column decoders YDC1, XDC1 allow one or more words comprising several memory cells belonging to a same line to be selected. Decoders XDC1, YDC1 are controlled by an address register AREG allowing a word at the intersection of a line and a group of columns to be selected. The memory array CELM comprises a bit line BL for each column of memory cells, a word line WL for each line of memory cells and a gate control line CGL for each word column, each gathering several bit lines. Decoders XDC1, YDC1 are powered by a voltage VPP, VPE, VPW by a high voltage generation circuit HVG1, and control the memory cells for reading, programming and erasing by supplying voltages adapted to the bit lines BL, the gate control lines CGL for decoder XDC1 and the word lines WL for decoder YDC1. For reading, the voltage VPP is equal to the supply voltage of the memory, and for programming and erasing, the voltage Vpp is equal to a high voltage, around 15 V.
Some memories have a burn-in test mode. To that end, they comprise a mode control circuit TMC1 to place the memory either in burn-in test mode, or a normal operating mode as a function of a test signal TST supplied to the memory. Circuit TMC1 controls circuit HVG1 and decoder YDC1, in particular to adjust the value of high voltage VPP as a function of the operating mode.
FIG. 2 shows a memory cell MC of the memory array CELM. In FIG. 2, each cell MC comprises an access transistor AT and a floating gate transistor FGT connected in series, the drain of transistor AT being connected to a bit line BL, and the source of transistor FGT being connected to the ground. The gate of transistor AT is connected to a word line WL and the gate of a gate control transistor CGT whose drain is connected to a gate control line CGL, and whose source is connected to the gate of transistor FGT. To program and erase the cell MC, transistors AT and CGT must be able to support the high voltage generated by circuit HVG1.
FIGS. 3A, 3B show a bit line latch of decoder XDC1. The bit line latch comprises two inverters mounted back-to-back, each formed by a high voltage P-channel MOS transistor, referred to as P1, P2, and a high voltage N-channel MOS transistor, referred to as N1, N2. Transistors P1, P2 receive voltage VPP on their source and their well bias terminal. The sources of transistors N1, N2 are connected to a low voltage line SWG. The drains of transistors P1, N1 and the gates of transistors P2, N2 are connected to the low voltage line SWG through an N-channel MOS transistor referred to as N3, whose gate is controlled by a reset signal RST. The drains of transistors P1, N1 and the gates of transistors P2, N2 are also connected to the gate of an N-channel MOS transistor referred to as N6, receiving on its drain a write command voltage VPW and whose source is connected to a bit line BL. The gates of transistors P1, N1 and the drains of transistors P2, N2 are connected to the low voltage line SWG through two N-channel MOS transistors referred to as N4, N5 connected in series. The gate of transistor N4 is controlled by a word column selection signal COL and the gate of transistor N5 is controlled by a data signal DT supplying the value of a bit to be written in a selected memory cell MC. Therefore, a bit line BL can be subjected to the high voltage only if the corresponding bit line latch is in the active state, if the data to be programmed DT is at 1, and if the corresponding column is selected (signal COL at 1). In some memories, the sources of transistors N3 and N5 may be connected to the ground GND.
FIG. 3A shows the latch in normal operation, in the reset state during a programming or write cycle. This state is previously reached by the temporary switching of transistor N3 to the conductive state, after a pulse of signal RST, maintaining transistors N4 and N5 in the blocked state (signals COL and DT at 0). During the pulse of signal RST, the drains of transistors P1, N1 and the gates of transistors P2, N2 receive the voltage SWG. Transistors P1 and N2 therefore switch to the blocked state, while transistors P2, N1 switch to the conductive state. The voltage SWG may be chosen different from zero, for example equal to 3 V, so as to limit the drain-well and drain-source voltages of transistors P1, P2 and drain-source voltages of transistors N1, N2. In practice, voltage SWG may not be higher to avoid programming non-addressed memory cells. When voltage VPP is set at the programming value (for example 15 V), transistors P2 and N1 are subjected to a maximum gate oxide stress voltage of 15−3=12 V.
FIG. 3B shows the latch in normal operation, in the active state during a programming or write cycle. This state is previously reached by temporary and simultaneously switching transistors N4 and N5 to the conductive state, after a pulse of signals COL and DT, while maintaining transistor N3 in the blocked state. During the pulse of signals COL and DT, the gates of transistors P1 and N1 and the drains of transistors P2, N2 receive the voltage SWG. Transistors P1 and N2 switch to the conductive state, while transistors P2, N1 switch to the blocked state. When voltage VPP is set to the programming value, transistors P1 and N2 are subjected to a maximum gate oxide stress voltage of 15−3=12 V.
The gate control line latches CGL of decoder XDC1 and the word line latches WL of decoder YDC1 have architectures similar to that of the bit line latch previously described.
To reduce circuit failure rate due to gate oxide breakdown of high voltage transistors, it is known to subject these circuits, at the end of manufacture, to burn-in tests that subject the gate oxides of high voltage transistors to sufficiently high test voltages below the intrinsic breakdown voltage of these gate oxides. The aim of these tests is to prematurely make weak microelectronic structures break down, so as to discard faulty or insufficiently robust circuits, and thus avoid them from being prematurely faulty during their use. A burn-in test is all the more efficient to discard the circuits having manufacture defects as test voltages are much higher than the voltages applied in normal operation, even near the intrinsic breakdown voltage of the gate oxides of high voltage transistors. However, the test voltages should not be chosen too close to this intrinsic breakdown voltage to avoid discarding circuits having acceptable defects.
FIGS. 4A, 4B show the bit line latch previously described, respectively in the reset state and the active state, burn-in test voltages being indicated. In burn-in test, voltages VPP and SWG are set to values allowing transistors P1, P2, N1, N2 to be subjected to a maximum gate oxide stress voltage without exceeding a breakdown threshold voltage of transistors P1, P2. In the example of FIGS. 4A, 4B, voltage VPP is set to 14 V and voltage SWG to 0 V. The weakness of P-channel MOS transistors formed in a well, is their drain-well junction which cannot admit more than 14 V in the blocked state. At voltages superior or equal to this value, leaks may also appear between the drain and source of these transistors. It is therefore not possible to subject these transistors to voltages significantly higher than normal operating voltages (VPP−SWG=12 V). However, the weakness of N-channel MOS transistors is between the drain and source, whose voltage cannot exceed 17 V in the blocked state.
When the latch is in the reset state shown by FIG. 4A, transistors P1 and N2 are blocked, while transistors P2 and N1 are conductive. The transistors whose gate oxides are subjected to a voltage stress of 14 V are therefore the conductive transistors P2, N1 (surrounded by a dotted line).
When the latch is in the active state shown by FIG. 4B, transistors P1 and N2 are conductive, while transistors P2, N1 are blocked. The transistors whose gate oxides are subjected to a voltage stress of 14 V are therefore the conductive transistors P1, N2 (surrounded by a dotted line). Transistor N6 which is subjected to voltage VPP, is also conductive. If the voltage VPW is equal to 0, this transistor is also subjected to a gate oxide stress voltage at 14 V.
Although the gate oxides of transistors considered to be of sufficient quality may support 17 V, it is not possible to go beyond 14 V due to the presence of P-channel transistors in the blocked state whatever the state of the circuit.
To compensate for the small difference between test voltages and normal operation voltages, it is known to increase the time during which each transistor to be tested is subjected to a test voltage. This solution also has a limit since it cannot be considered to penalize production rates by increasing burn-in test durations beyond an acceptable limit.